This application claims priority of European Patent Application No. 98306713.3, which was filed on Aug. 21, 1998.
This invention relates generally to the field of phase correlation and, more particularly, to correlating the phases of a clock signal and data signals.
In high bit rate networks frequency synchronous lower bit rate data signals are combined by multiplexers to form the high bit rate signal. Often hierarchies of multiplexers are used to form the high bit rate signal, i.e., multiplexers of different bit rate levels are concatenated. In a first hierarchy from low bit rate data signals medium bit rate data signals are formed which then are multiplexed to a high bit rate data signal by a multiplexer of a second hierarchy. Usually all data signals of a common hierarchy are frequency synchronous. After forming the medium bit rate data signals, multiplexing them to the high bit rate data signal causes a problem, because the medium bit rate data signals often show a phase deviation from the common frequency used for multiplexing, i.e., a phase deviation from a common clock signal.
The phase deviation can be adjusted by using a phase correlator and a delay line for phase adjusting the medium bit rate data signals to the common clock signal of the medium bit rate data signals. But adjusting the phase deviation for the medium bit rate data signals causes problems, because an apparatus for adjusting the phase deviations of the medium bit rate data signals to the common clock signal has to operate at relatively high frequencies.
According to the principles of the invention, an apparatus is provided for correlating phases of a clock signal and data signals to adjust for phase deviations in a network having multiplexers of a first hierarchy concatenated with multiplexers of at least one higher hierarchy. More specifically, the apparatus according to the principles of the invention includes means for correlating phases of the clock signal and data signals of the higher hierarchy, to generate control signals indicative of a phase deviation of the data signals to the clock signal of the higher hierarchy, delay means controlled by the control signals to adjust for the phase deviation of the data signals to the clock signal of the higher hierarchy, whereat the delay means at least delay one input signal of each multiplexer of a lower hierarchy.
An advantage of the present invention is that it allows correction of the phase deviation of each data input of the multiplexer of the highest hierarchy separately. Another advantage of the present invention is that the phase adjustment is effected at a location in the multiplexing hierarchy which is at least one hierarchical level below where the phase deviation occurs. As the adjustment of the phase deviation thus is effected for a lower bit rate signal, less timing critical circuitry can be used to achieve the phase adjustment, as the clock phase margin at re-timing D-flip-flops usually used in the multiplexers is more relaxed.